3rd march 2010

Xilinx is looking for enthusiastic individuals who want to be on the cutting edge of technology, interact with customers on a daily basis and at the same time contribute to Xilinx's market leadership in high speed IO technology. System IO FAEs frequently interface with customers to help them architect and implement systems using Xilinx IO technology. System IO FAEs will also interact with other specialists and factory engineers for product support and product improvement feedback.

Primary role is the technical selling and support of Xilinx System IO connectivity solutions at the system-level for global and strategic accounts. Research, evaluate and conduct detailed system architecture analysis in order to articulate Xilinx advantages and present Xilinx solutions. Drive design wins at global and strategic accounts, working with sales representatives and Xilinx sales management and FAEs. Evangelize and articulate Xilinx high-speed IO solutions through technical seminars, presentations and demonstrations. As a senior level position, the Specialist is a highly motivated self-starter and requires little day-to-day supervision.





Desired Profile      


Requirements

•      Signal Integrity Knowledge

-      Understand channel loss, impedance discontinuity, and PCB design techniques for multi-gigabit signaling

-      Understand how the effects of transmit preemphasis and receive equalization are used to compensate for channel characteristics

-      Have hands on experience with measurement equipments (high speed scopes, TDR) and board debug

-      Experience with analog simulation tools for modeling transmission lines

-      Ability to assist customers with board design review both on usage of Xilinx FPGA and provide advice on high speed channel design

-      Working knowledge of H-Spice, Hyperlynx, Ansoft, Spectraquest

-      Understand common SERDES features such as encoding/decoding, byte-alignment, clock correction, channel bonding, elastic buffer

-      Understand PHY/MAC layer protocol for common interfaces such as Sonet and Ethernet

-      Ability to promote and support interface protocol IP cores such as Ethernet MAC, FibreChannel MAC

-      In-depth knowledge of high-speed standard digital communications protocols: Gigabit Ethernet, Fibre Channel, XAUI, SONET/SDH, SPI 4.2, SFI 4.1, Serial RapidIO, GFP, PCI Express, SDI, HD-SDI, AS

•      Design Knowedge

-      Ability to put together demo designs and reference designs for customer using VHDL or Verilog

-      Have sufficient knowledge on digital design issues such as system level clock planning and buffer designs



Excellent communication and presentation skills and experience working with customers in a pre-sales capacity.

Minimum of BSEE (MSEE preferred) with 6+ years of experience.



Traveling is required



Experience       5 - 10 Years
Industry Type      Semiconductors/ Electronics
Role      Sr. Design Engineer
Functional Area      Engineering Design, R&D
Education       UG - B.Tech/B.E. - Any Specialization
PG - Any PG Course - Any Specialization
Location       Hyderabad / Secunderabad
Keywords       IO, Buffers, FAE, CAE, Hspice, SERDES, PHY
Contact       Ravi Kiran
Xilinx India Technology Services Pvt Ltd
Unit No.04-01, 4th floor Block1, Cyber Pearl
Hitec City, Madhapur
HYDERABAD,Andhra Pradesh,India 500081
Telephone       91-40-23144000
Website       Login or Register to view attachments

Date july 06 2010

Designation       Sr. Engineer - Physical Design (Highspeed DDR / Timing)


Job Description      
This position will be critical to shaping the next generation of FPGA products from Xilinx, the leader in FPGAs. The successful candidate for this position will join a technology leader, a rapidly growing organization and be an integral member of a skilled and motivated team. The job will involve building the next generation devices for Xilinx using a leading edge SoC and FPGA implementation flow. The successful candidate will be responsible for executing DFT activities for next generation FPGA devices.

Job Responsibilities



• Responsible for executing various physical design activities for SoC implementation

• Responsibilities include implementation of high speed interfaces like DDR2/3, RGMII etc.

• Close Interaction with CAD, physical verification and closure teams.



Desired Profile      
Job Requirements

• 4+ years hands-on experience with timing closure of high-speed interface/DDR integration

• Experience with chip level physical design – CTS, routing, ECO flows. Synopsys ICC experience is highly desired.

• Very good understanding of front-end SoC/ASIC design and implementation including Synthesis and STA.

• Hands-on experience with few of the DSM SoC/ASIC methodologies including advanced DFM, DFT, OCV, IR Drop and signoff methodologies

• Should have participated in successful tapeouts of ASIC chips at 65/45nm or below

• Should be motivated, self-starter.

• Excellent communication skills

• M.S/M.Tech or BTech/BE/BSEE with 6+ years of experience.



Experience       6 - 11 Years

Contact       Ravi Kiran
Xilinx India Technology Services Pvt Ltd
Unit No.04-01, 4th floor Block1, Cyber Pearl
Hitec City, Madhapur
HYDERABAD,Andhra Pradesh,India 500081
Telephone       91-40-67214110
Email      ravikir@xilinx.com

Xilinx leads the Programmable Logic Device (PLD) market - one of the fastest growing segments of the semiconductor industry. Founded in 1984 and headquartered in San Jose, California, we are a $1.9 billion company with an employee base of over 3300 professionals across our global offices. We take pride in nurturing innovation and providing our employees with a values-driven and rewarding workplace.