The steps are as follows
1. Starting material n-doped single crystalline epi-wafers.
2. Growth of initial thin implantation oxide.
3. Mask PWELL for implantation of p-dopants.
4. High temperature drive-in of pwell and oxidation.
5. Removal of oxide.
6. Growth of thin pad oxide followed by nitride deposition.
7. De
ne active area with OXIDE mask.
8. Local oxidation to form
eld oxide, surrounding the active area.
9. Growth of thin gate oxide.
10. Deposition of poly-silicon.
11. Blanket implantation of poly to set the poly-resistor sheet resistance.
12. High dose implantation of poly-silicon. Protect resistor areas with RES mask.
13. Mask POLY and etch gate and poly-resistor structures.
14. Self-aligned implantation of NPLUS for source/drain of NMOS.
15. Self-aligned implantation of PPLUS for source/drain of PMOS.
16. Activation and di
usion of source and drain dopants.
17. Deposition of CVD-oxide.
18. Mask CONTACT and etch contact holes.
19. Sputter deposit
rst metalization, Al/Si.
20. Pattern METAL1 and etch the
rst metal layer.
21. Deposit Silicon-Nitride.
22. Pattern CAP and etch Silicon-Nitride.
23. Deposit inter layer oxide.
24. Mask VIA and etch.
25. Sputter deposit second metalization, Al/Si.
26. Pattern METAL2 and etch the second metal layer.
27. The process is
nished by cap-layer deposition and etch of pad-openings.
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